An extension to instruction set architecture (ISA) provides interfaces for software to work with transactional memory (TM) support. The basic goal is to speed-up multi-threaded workloads by providing hardware schemes that let these workloads execute certain group of operations through lock elision. A commercial example of TM is Hardware Lock Elision (HLE) and Restricted Transactional Memory (RTM).
HLE extensions add two new instruction prefixes, XACQUIRE and XRELEASE. The basic concept is that the thread executes XACQUIRE, an arbitrary stream of instructions plus XRELEASE. Logically, this section can be seen as “lock( );Instructions( );unlock( )”. Even though one thread may be executing this section, the other threads see this section as free. In case a violation (meaning other threads enter the critical section) is detected by the processor, the inflight transaction is aborted and the thread restarts the instructions stream from the XACQUIRE. All the instructions are committed after XRELEASE are executed with no violation detected.
TSX is a good hardware-based solution to improve software systems that are heavily threaded accessing small but frequently shared streams of address and code. However, this mechanism is applied within a coherent domain (i.e. multi-socket system connected through UPI). With increasing volumes of datasets, transactional software such as databases, need to be able to operate on several shared memory systems over a high speed interconnect, such as a fabric. There may be several 10s of these systems connected via the interconnect, and they will span different coherent domains (a domain could be a single system or a group of systems).